BARCELONA, Spain, March 20, 2019 (GLOBE NEWSWIRE) --
eSilicon, a leading provider of FinFET-class ASICs, market-specific IP platforms and advanced 2.5D packaging solutions, with the Polytechnic University of Catalonia, Barcelona, Spain are presenting two papers on advanced floor planning techniques at DATE 2019, Florence, Italy.
Alex Vidal-Obiols, Jordi Cortadella, Jordi Petit, Department of Computer Science, Universitat Politècnica de Catalunya.
Marc Galceran-Oms, Ferran Martorell, eSilicon EMEA, Barcelona, Spain.
RTL-Aware Dataflow-Driven Macro Placement
This paper proposes a novel multi-level approach for macro placement of complex designs dominated by macro blocks, typically memories. Using the hierarchy tree, the netlist is divided into blocks containing macros and standard cells and their dataflow affinity is inferred considering the latency and flow width of their interaction. This information, known by the RTL designer, is often lost during physical synthesis. The layout is represented using slicing structures and generated with a top-down algorithm capable of handling blocks with hard and soft components, aimed at wirelength minimization. This approach outperforms commercial tools and handcrafted results. These floor plans provide an excellent starting point for physical design and can significantly reduce turn-around time.
Tuesday, March 26
3:30 PM Session 3.4.4
Design Mapper: Dataflow Analysis for Better Floor Plans
RTL-level information in the netlist provides insight on circuit structure, but it is usually not sufficiently exploited at physical design. Design Mapper captures hierarchy and array information from the netlist to automatically extract the dataflow relations between blocks and macros in the design. The information helps find better macro placements and reduces turn-around time.
Friday, March 29
4:30 PM Session W04.12.2
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