Multiple Mentor product lines now certified on TSMC’s most advanced processes

September 27, 2019 -- Today at the TSMC 2019 Open Innovation Platform® (OIP) Ecosystem Forum, Mentor, a Siemens business, announced a broad array of recently certified tools, compelling new functionalities and other foundry-specific enablement measures on TSMC’s most advanced processes intended to benefit mutual Mentor/TSMC customers and help to further expand TSMC’s growing ecosystem.

TSMC has once again certified Mentor’s Calibre nmDRC™, Calibre nmLVS™, Calibre YieldEnhancer, Calibre PERC™ and Analog FastSPICE (AFS™) Platform, now for the latest version of DRM and SPICE on TSMC’s N5, N7+, N5P and N6 processes. With these certifications, Mentor’s AFS platform now supports the mobile and high-performance computing (HPC) design technologies on TSMC’s process technologies, allowing Mentor customers targeting analog, mixed-signal and radio frequency (RF) designs to verify their chips with confidence in the latest TSMC 5nm and 7nm processes.

“These new certifications on TSMC’s process technologies are very valuable to our growing ecosystem, enabling our customers to achieve successful silicon innovations on the most advanced processes for the mobile and HPC applications,” said Suk Lee, TSMC senior director, Design Infrastructure Management Division. “We’re very pleased with the result of our ongoing collaboration with Mentor in certifying several key products for our most advanced processes, and look forward to the compelling end-products that they will inevitably enable.”

Mentor today also announced that Mentor’s Calibre YieldEnhancer, the platform used for SmartFill functionality, now offers additional features in support of the latest TSMC technologies. Mentor’s added features include easier and simpler modification of fill shapes, together with last-minute ECO (Electronic Change Order) design changes. 

“Mentor has a long track record of collaborating with TSMC to establish highly innovative solutions for even the most complex of process technology challenges,” said Joe Sawicki, executive vice president for Mentor’s IC Segment. “Mentor looks forward to continuing its successful partnership with TSMC for the ongoing benefit of our many mutual customers.”

Visit Mentor at TSMC’s North America Forum

Mentor invites engineers planning to attend TSMC’s Open Innovation Platform Ecosystem Forum in Santa Clara to visit booth #608, as well as attend the below Mentor-led technical sessions:

  • HPC & 3DIC Track, 11:00 – 11:30, Calibre in the Cloud – A case study with AMD, Mentor and TSMC; a Microsoft, AMD, and Mentor co-presentation.
  • HPC & 3DIC Track, 15:30 – 16:00, Large Scale Silicon Photonic Interconnects for Mass Market Adoption; an HPE and Mentor co-presentation.
  • Mobile & Automotive Track, 13:30 – 14:00, Comprehensive ESD/Latch-up reliability verification for IP and SoC Designs; an NXP, Silicon Frontline and Mentor co-presentation.
  • IoT & RF Track, 17:00 – 17:30, Optimize SoC designs while enabling faster tapeouts by closing chip integration DRC issues early in the design cycle; a MaxLinear and Mentor co-presentation.
  • Mobile & Automotive Track, 13:00 – 13:30, Overcome time-to-market and resource challenges: Hierarchical DFT for advanced node SoC design and production; a Mentor presentation.



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