LOUISVILLE, Colo., Jan. 23, 2019 (GLOBE NEWSWIRE) -- The 2019 Design and Verification Conference and Exhibition (
DVCon) U.S., now in its 31st year, has much to offer attendees over the course of the four-day program including 39 in-depth technical papers, four tutorials, 25 posters, eight short workshops, two panels and a thought-provoking keynote address. The
program is now available online and
advance registration is available through January 28. DVCon U.S., sponsored by
Accellera Systems Initiative, will be held February 25 – 28, 2019 at the DoubleTree Hotel in San Jose, California.
“I think attendees will be very impressed by the depth and breadth of our technical program this year,” stated Tom Fitzpatrick, DVCon U.S. 2019 Technical Program Chair. “In addition to the key technical topics our attendees have come to expect from DVCon, we had many submissions on new topics this year that will be very compelling and beneficial to our audience. We’ll have two paper sessions on Portable Stimulus, as well as sessions on applying “Big Data” to verification, formal verification, hybrid verification environments and many other valuable topics. With two great panels on Deep Learning and RISC-V, there are many intriguing topics for attendees to choose from as they review the detailed program.”
“As in years past, the tutorials and short workshops cover a wide variety of topics,” commented Vanessa Cooper, DVCon U.S. 2019 Tutorial Chair. “There are sessions on UVM, Formal Verification, Portable Stimulus, Safety, and Machine Learning just to name a few. Conference goers will easily find multiple sessions of interest to attend.”
Program Highlights include:
- A UVM-focused tutorial on Monday, February 25 titled, “Gain Valuable Insight into the Changes and Features that Are Part of the New IEEE 1800.2 Standard for UVM and How to Make the Most of Them,” presented by Cliff Cummings as part of Accellera Day.
- A Monday afternoon short workshop from Accellera focused on SystemC, as well as eight sponsored short workshops throughout the week. The short workshop format is an exciting addition to the program that allows attendees more access to in-depth presentations on a wide variety of topics from multiple perspectives.
- An informative keynote address, “ Thriving in the Age of Digitalization,” on Tuesday, February 26 from 1:30pm-2:30pm in the Oak/Fir Ballroom presented by Fram Akiki, Vice President, Electronics & Semiconductor Industry for Siemens PLM Software. Mr. Akiki will discuss why it’s important to have an integrated digitalization strategy to succeed in today’s semiconductor market.
- 25 Posters will be presented on Tuesday, February 26 from 10:20am-noon.
- Two panel sessions on Wednesday, February 27:
1. The panel, “Verification and Compliance in the Era of Open ISA—Is the Industry Ready to Address the Coming Tsunami of Innovation?” at 8:30am will explore the RISC-V instruction set architecture’s features, benefits and challenges for processor IP and SoC development. More information on the panel, including the list of panelists, can be found here.
2. “Deep Learning—Reshaping the Industry or Holding to the Status Quo?” at 1:30pm will examine how AI and deep learning will reshape the semiconductor industry. More information on the panel, including a list of panelists, can be found here.
- We encourage you to cast your votes throughout the conference for the Best Paper and Best Poster. The awards will be presented at the reception on Wednesday, February 27 at 4:45pm.
sponsored tutorials on Thursday, February 28:
1. “ Data-Driven Verification: Driving the Next Wave of Productivity Improvements,” sponsored by Cadence Design Systems
2. “ Tackling the Complexity Problem in Control and Datapath Designs with Formal Verification,” sponsored by Synopsys
3. “ Nex Gen System Design and Verification for Transportation,” sponsored by Mentor, A Siemens Business
Attendees will have an opportunity to socialize and meet with peers and experts in the design and verification community throughout the conference as well as during the Expo, which will be held Monday from 5:00pm to 7:00pm and Tuesday and Wednesday from 2:30pm to 6:00pm.
For the complete DVCon U.S. 2019 schedule, including a list of tutorials, papers, short workshops, panels, posters, sponsored luncheons and events, visit https://dvcon.org/agenda. To view the videos from the DVCon U.S. 2018 Accellera Day tutorials, visit http://www.accellera.org/resources/videos/.
Visit https://dvcon.org/rates for more information on registration.
DVCon is the premier conference for discussion of the functional design and verification of electronic systems. DVCon is sponsored by Accellera Systems Initiative, an independent, not-for-profit organization dedicated to creating design and verification standards required by systems, semiconductor, intellectual property (IP) and electronic design automation (EDA) companies. In response to global interest, in addition to DVCon U.S., Accellera also sponsors events in China, Europe and India. For more information about DVCon U.S., please visit www.dvcon.org. Follow DVCon on Facebook https://www.facebook.com/DvCon or @dvcon_us on Twitter or to comment, please use #dvcon_us.
|For more information, please contact:
|Nannette Jordan||Barbara Benjamin|
|MP Associates, Inc.||HighPointe Communications|
|Email Contact||Email Contact|