Nanometer designs contain millions of devices and operate at very high frequencies. To meet the challenges posed by such large-scale circuits, techniques have been developed to represent integrated circuit designs at various levels of abstraction. According to these techniques, an integrated circuit design may be represented by an electrical schematic containing devices and nets interconnecting the devices and by geometric layout data that describes patterns of regions or elements to be formed in and/or on an integrated circuit substrate (e.g., wafer). Techniques for managing highly integrated circuit designs include hierarchical design techniques. These hierarchical techniques can be essential to the efficient performance of computer-assisted integrated circuit design verification. Such verification may include operations to perform layout versus schematic comparison (LVS) using computer-based design tools.
Today, any mismatches are corrected manually by a layout designer. The layout designer first must find the correct connection and then determine how to create the correct electrical connection in the mask layout database. This process of adding/modifying an electrical connection(s) may take several hours or days to complete. Furthermore, the layout designer may introduce design rule errors in the mask layout database when adding the new connection. Eliminating the design rule errors may additionally require several more hours or days and thus, increase the design time for the integrated circuit furthermore. Using Sigma these electrical connection mismatches are automatically eliminated within minutes which results in a massive reduction in the entire chip design time. In addition, the tool includes an Auto-Correct option to automatically correct a completed IC layout block. One of the key advantages of the software is its statistical analysis and violations mapping feature. The program prepares violation statistics including a detailed report of each violation and an automatic correction solution(s). Upon user's approval, Sigma automatically corrects the violation(s), saving hours or days of manual work. After the correction, Sigma rechecks the microchip block to verify that all violations are fixed.
"The new method and system deployed via Sigma supports the industry's newest manufacturing design processes and standards. With Sigma, designers can potentially save weeks and months of IC custom layout design time. This tool especially benefits Analog and Mixed Signal design styles and can eliminate the stress and time of solving a major challenge," stated Dr. Rittman, the Company and Alpha CTO.
About Gopher Protocol Inc.
Gopher Protocol Inc. (
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Contact: Dr. Danny Rittman CTO Gopher Protocol Inc. VM Only 888-685-7336 Media: firstname.lastname@example.org