Synopsys IC Compiler II Sets the Bar in Quality-of-Results

Graphcore Adopts IC Compiler II for Implementing their Machine-Learning Processor Chip

MOUNTAIN VIEW, Calif., Feb. 21, 2017 — (PRNewswire) —  

Highlights:

  • Technology developments in latest release cement IC Compiler II's QoR leadership by   delivering 5 percent better area, 5 percent better timing QoR and up to 20 percent reduction in power.
  • With 19 of the 20 top IC companies already using IC Compiler II as their place-and-route solution, momentum continues towards market leadership.
  • Superior QoR delivered by IC Compiler II enables Graphcore to design their first, ultra large, machine learning processor chip at 16FF process technology.

Synopsys, Inc. (Nasdaq: SNPS) today announced immediate availability of the latest release of its flagship IC CompilerTM II place-and-route system, continuing the trend of unabated technology innovation which has enabled more than 100 customers to engage in over 250 production designs encompassing several thousand physical partitions. The latest release includes several key technologies to deliver superior quality-of-results (QoR) and faster time-to-results (TTR) for performance-critical designs.

With capabilities like automatic placement-clustering, advanced logic structuring, analytical clock-and-data optimization and new algorithms for power optimization, the latest release offers up to 5 percent better timing, 5 percent smaller area and 20 percent power savings. Superior place-and-route technology has led to Graphcore, a UK-based artificial intelligence startup, to adopt IC Compiler II as their implementation platform for designing their first and ultra large, machine learning processor chip.

"We are designing a completely new type of processor – an Intelligent Processor Unit (IPU) designed to help customers accelerate the development of machine intelligence products and services," said Simon Knowles, CTO of Graphcore. "With an extremely large design being built-from scratch, fast and predictable QoR throughout the design flow is key for our success. We believe IC Compiler II's powerful infrastructure and superior technologies will enable us to achieve our goals and bring our product to market on time."

The latest release of IC Compiler II provides key new technologies specifically targeted at increasing QoR, TTR, as well as advanced-node enablement. Concurrent Clock-and-Data (CCD) Optimization, a key technology for high-performance designs, has been significantly enhanced with a new, solver-based, multi-objective engine capable of trading-off timing, area and power over an expanded solution space with minimal runtime impact. CCD also benefits from new technology specifically focused on power reduction. Other optimization technologies have been deployed in both the pre-route and post-route stages of design. During pre-route, enhanced global-route-based optimization provides significantly improved pre- to post-route correlation with better timing. In addition, advanced buffering for high-fanout nets improves QoR for the most challenging designs. Post-route, the optimization has been enhanced with two key new technologies: optimization driven by path-based analysis (PBA) and new advances in leakage power optimization.

In addition to QoR, several new technologies have also been introduced to help accelerate TTR. For example, automatic placement clustering provides an optimized initial placement, leading to less variability between runs, and thus reducing the time needed to achieve an optimal placement. Another example is automatic-max-density technology which increases productivity by automatically determining the targets for cell spreading during placement, providing optimal wire length, timing and congestion.

"IC Compiler II has rapidly established itself as the place-and-route solution of choice for high-performance designs, and the recent adoption by innovative startups like Graphcore exemplifies this trend," said Sassine Ghazi, Senior VP and Co-GM, Design Group at Synopsys. "Key technology enhancements in the latest release of IC Compiler II focus on efficiently delivering excellent QoR for performance-critical designs, helping our customers get more differentiated products to market quickly."

About Synopsys

Synopsys, Inc. (Nasdaq: SNPS) is the Silicon to Software™ partner for innovative companies developing the electronic products and software applications we rely on every day. As the world's 15th largest software company, Synopsys has a long history of being a global leader in electronic design automation (EDA) and semiconductor IP and is also growing its leadership in software security and quality solutions. Whether you're a system-on-chip (SoC) designer creating advanced semiconductors, or a software developer writing applications that require the highest security and quality, Synopsys has the solutions needed to deliver innovative, high-quality, secure products. Learn more at www.synopsys.com.

Editorial Contact:
Carole Murchison
Synopsys, Inc.
650-584-4632
Email Contact

 

To view the original version on PR Newswire, visit: http://www.prnewswire.com/news-releases/synopsys-ic-compiler-ii-sets-the-bar-in-quality-of-results-300410230.html

SOURCE Synopsys, Inc.

Contact:
Synopsys, Inc.
Graphcore
Web: http://www.synopsys.com




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