ZTE Achieves Performance Breakthrough for Deep Learning with Intel FPGAs

January 24, 2017 - Intel and ZTE, a leading technology telecommunications equipment and systems company, have worked together to reach a new benchmark in deep learning and convolutional neural networks (CNN). The technology is what many companies in Internet search and artificial intelligence are trying to advance, and includes picture search and matching, as one example.

“Perception, such as recognizing a face in an image, is one of the essential goals of the ZTE 5G System,” said Duan Xiangyang, vice president of ZTE Wireless Institute. “Deep learning technology is very important as it can enable such perception in mobile edge computing systems, thus making ZTE’s 5G System smarter.”

The test took place in Nanjing City, China, where ZTE’s engineers used Intel’s midrange Arria® 10 FPGA for a cloud inferencing application using a CNN algorithm.

ZTE has achieved a new record – beyond a thousand images per second in facial recognition – with what is known as “theoretical high accuracy” achieved for its custom topology. Intel’s Arria 10 FPGA accelerated the raw design performance more than 10 times while maintaining the accuracy.

The Arria 10 FPGA provides up to 1.5 teraflops (TFLOPs) single precision floating-point processing performance, 1.15 million logic elements and more than a terabit-per-second high-speed connectivity.

Such deep learning designs can be seamlessly migrated from the Arria 10 FPGA family to the high-end Intel Stratix® 10 FPGA family, and users can expect up to nine times performance boost.

Besides the impressive increase in performance, the team at ZTE Wireless Institute sped design time with the use of the OpenCL programming language.

“With the Intel reference design, and using the Intel SDK for OpenCL to program the FPGA, our development time was greatly shortened,” said Xiong Xian Kui, chief engineer at ZTE Wireless Institute. “We are pleased with the benchmark achieved and thank the Intel Programmable Solutions Group for supporting our project.”

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Configuration:

The benchmark was achieved on a server holding 4S Intel Xeon E5-2670v3 processors running at 2.30GHz, 128GB DDR4; Intel PSG Arria 10 FPGA Development Kit with one 10AGX115 FPGA, 4GB DDR4 SODIMM, Intel Quartus Prime and OpenCL SDK v16.1.




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