Arasan Announces MIPI C-PHY IP Core compliant to the latest C-PHY v1.1 Specifications

Dec 1, 2016, San Jose, CA - Arasan today announced the immediate availability of its MIPI C-PHY IP Core fully compliant to the C-PHY specification Version 1.1 while also being compliant to the D-PHY 1.2 Specification. It supports the MIPI® Camera Serial Interface (CSI-2) and Display Serial Interface (DSI-2) protocols. It is a universal PHY that can be configured as a transmitter, receiver or both. This IP core is specially optimized for area and power.

The camera is the top selling feature in Smartphones today and megapixel count and image quality will continue to increase as Smartphone rapidly become the primary camera for most users.

Cameras are a critical element in the Automobile SoC market. The MIPI CSI Camera Interface is being adopted as the primary interface to optical cameras, radars and Lidar to enable autonomous driving features. Arasan’s MIPI CSI, DSI and DPHY IP’s have been used widely in the Automotive markets with stringent quality and failure recovery requirements.

The C-PHY is targeted toward high resolution displays to more efficiently transfer data with lower power consumption and die size compared to the DPHY. It utilizes a lower signally rate than the MIPI D-PHY but provides support for low-cost, low-resolution image sensors, sensors offering up to 60 megapixels; and 4K video display panels.

C-PHY achieves a peak bandwidth of 2.5 Gsymbol/s at 2.28 bits/symbol, or 17.1 Gbps over a 9-wire interface, compared to compared to the D-PHY v1.1 peak transmission rate of 1.5 Gbps/lane or 6 Gbps over a 10 wire - 4 lane interface.

The Arasan ComPHY supports C-PHY and MIPI D-PHY for backward compatibility with existing SoC designs. The ComPHY IP offering from Arasan utilizes a patent pending architecture that optimizes the C-PHY and D-PHY design for ultra low power and area.

“We utilized our 8+ years of experience to develop a new patent pending architecture for the PHY providing robust ESD performance, reduced Monte-Carlo variations, and optimized high-speed operation. The novel configurable architecture enhances the industry's leading IP core in terms of power, area and reliability,” said Sridhar Shashidharan, Analog IP Architect at Arasan.

Arasan’s whitepaper comparing CPHY vs. DPHY can be downloaded  here.   

Availability

The C-PHY is immediately available for the TSMC 28nm and other 28nm processes and will be available on the 16nm process early Q1 2017. Test Chips and Development Platforms will be made available to prospective customers.

About Arasan

Arasan Chip Systems is a leading provider of Total IP Solutions for mobile and the next generation of Smart applications from home to automobile. Arasan’s high-quality, silicon-proven, Total IP Solutions include digital IP cores, analog PHY interfaces, verification IP, hardware verification kits, protocol analyzers, software stacks and drivers, and optional customization services for Ethernet, MIPI, PCIe, USB, UFS, SD, SDIO, eMMC, and UFS. Arasan’s Total IP products serve system architects and chip design teams in applications that require silicon-proven, validated IP, delivered with the ability to integrate and verify both digital, analog and software components in the shortest possible time with the lowest risk. 

About the MIPI Alliance

MIPI Alliance (MIPI) develops interface specifications for mobile and mobile-influenced industries. Founded in 2003, the organization has more than 275 member companies worldwide, more than 15 active working groups, and has delivered more than 45 specifications within the mobile ecosystem in the last decade. Members of the organization include handset manufacturers, device OEMs, software providers, semiconductor companies, application processor developers, IP providers, test and test equipment companies, as well as camera, tablet and laptop manufacturers. For more information, please visit  http://www.mipi.org.




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