Plunify's InTime Design Optimization Software Supports Altera FPGAs and SoCs

LOS ALTOS, CA -- (Marketwired) -- Nov 12, 2014 -- Plunify® Pte. Ltd., provider of groundbreaking field programmable gate array (FPGA) software, today announced its InTime™ design optimization software provides support for Altera's FPGAs and systems on chip (SoCs).

Plunify's InTime software harnesses computing resources and machine learning to rapidly generate optimized strategies for solving design problems.

"We are pleased to have Plunify join our partner network," says Alex Grbic, director of software and IP marketing at Altera. "Working with companies like Plunify enables us to offer our customers a variety of complementary solutions."

Plunify's InTime software can provide Altera users a faster path to production. The InTime design optimization software evokes Altera's Quartus® II software to analyze designs and determine the best synthesis and place-and-route strategies. InTime has built-in intelligence to examine an FPGA design, derive correlations between the design, the FPGA device and the tool parameters, and subsequently provide users optimized strategies for synthesis and place-and-route. In one example, Huawei successfully deployed InTime in its production flow to close timing on multiple designs.

Introduced in June, InTime uses statistical modeling and machine learning to draw insights from the data to improve quality of results. Furthermore, InTime has the ability to accumulate knowledge that can be applied to subsequent designs, or re-applied to the same design after it has been modified.

"We are pleased to be part of the Altera ecosystem," remarks Harnhua Ng, Plunify's chief executive officer. "The evaluations we did with mutual customers and the benchmarking results show that InTime can be a valuable solution to analyze and manage multiple FPGA design compiles. Users appreciate InTime's machine learning feature because the engine gets better each time they run it."

About Plunify
Solutions from Plunify® Pte. Ltd. enable semiconductor chip designers to shorten product time to market and reduce development costs with no disruption to existing workflows. Its EDAxtend™ cloud platform and InTime™ timing closure tool help electronics companies meet FPGA design performance targets and significantly reduce their products' time to market. For more on Plunify's products, visit www.plunify.com.

Plunify is a registered trademark of Plunify Pte. Ltd. EDAxtend is a trademark of Plunify. Plunify acknowledges trademarks or registered trademarks of other organizations for their respective products and services.

For more information, contact:
Nanette Collins
Public Relations for Plunify
(617) 437-1822

Email Contact





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