Verific to Demonstrate Parser Platform at DVCon 2013 Expo

Eight Other DVCon Exhibitors Utilize Verific’s Software as Front-End to Analysis, Simulation, Verification, Synthesis, Emulation 

ALAMEDA, CALIF. –– February 19, 2013

WHO: Verific Design Automation, provider of SystemVerilog, Verilog and VHDL parsers

WHAT: Will exhibit at the DVCon 2013 Expo in Booth #505 and demonstrate its Parser Platform with support for SystemVerilog, Verilog, VHDL and UPF, and C++ and Perl application programming interfaces (APIs).

WHEN: Tuesday and Wednesday, February 26-27, from 3:30 p.m. until 6:30 p.m.

WHERE:  Doubletree Hotel in San Jose, Calif.

Other DVCon exhibitors using Verific’s software as the front end to their analysis, simulation, verification, synthesis and emulation tools include Aldec, Atrenta, Blue Peal Software, Calypto, Forte Design Systems, Jasper Design Automation, Real Intent, S2C and Synopsys.

Information about Verific can be found at www.verific.com.

The DVCon website address is: www.dvcon.org.

About Verific Design Automation

Verific Design Automation, with offices in Alameda, Calif., and Kolkata, India, provides parsers and elaborators for SystemVerilog, Verilog and VHDL. Verific’s software is used worldwide by the EDA and semiconductor community in synthesis, simulation, formal verification, emulation, debugging, virtual prototyping, and design-for-test applications, which combined have shipped more than 40,000 copies. Corporate headquarters is located at: 1516 Oak Street, Suite 115, Alameda, Calif.  94501. Telephone: (510) 522-1555. Facsimile number: (510) 522-1553. Email: Email Contact. Website:  www.verific.com. Follow Verific on Facebook: http://www.facebook.com/pages/Verific-Design-Automation/100448363329771.

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Verific Design Automation acknowledges trademarks or registered trademarks of other organizations for their respective products and services.




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