Digital Core Design introduces DT8051 – the world's most powerful tiny 8-bit CPU

Nov 1st, 2012 -- Digital Core Design, IP Core provider and a System on Chip design house, has introduced the DT8051. The newest IP Core from Poland is the world’s most powerful tiny 8051 available on the market. The complete system with peripherals and the DoCDTM debugger needs just 6 650 ASIC gates, when a standalone CPU utilizes little else than 3k gates.

The DT8051 is an area optimized tiny soft core of a single chip 8-bit embedded microcontroller, based on the most popular 8051 MCU. The Polish IP Core seems to be an excellent solution, also regarding to 32-bit ARM Cores, when even a plain M0 utilize more than 10000 gates. – In terms of  the cost & area of silicon-proven DT8051, not just other 8-bit MCUs, but also a 32-bit processor licensing comes close – says Tomek Krzyzak, the Vice President of Digital Core Design. Moreover, our DT8051 can run in very small FPGA devices or can be just a tiny fragment of a System-on-Chip ASIC - as the old saying goes: small is beautiful. A very low gate count area allows as well to run the core at high performance, up to 300 MHz in Hynix 0.18 library (equivalent performance to the original 80C51, clocked with 2400 MHz).

The DT8051 soft core is 100% binary-compatible with the industry standard 8051 8-bit microcontroller, but in comparison to its ancestor, DCD’s IP Core has a very low gate count architecture, giving 6 650 ASIC gates for the complete system with peripherals and the DoCDTM on-chip debugger. But the size wouldn’t mean anything, without an appropriate performance. – The DT8051 could be named a “mighty power” – says Piotr Kandora, a VP & Director of R&D at DCD. Dhrystone 2.1 benchmark program runs exactly 8.1 times faster, than the original 80C51 at the same frequency. So the performance results are more than 2 times higher than the nearest competitive designs.

The DT8051 includes a 2-wire DoCDTM on-chip debugger (TTAG), up to eight external interrupt sources, an advanced Power Management Unit, Timers 0&1, I/O bit addressable Ports, full duplex UART and interface for external SFR. Furthermore, DCD’s IP Core has a built-in support for the 2-wire TTAG interface - DCD Hardware Debug System, popular DoCDTM. This version of the debugger is dedicated for applications, where a number of external pins is limited.

The DT8051 is delivered with fully automated test bench and complete set of tests, allowing easy package validation, at each stage of SoC design flow.




Review Article Be the first to review this article


Featured Video
Latest Blog Posts
Jim SparksGISCafe Guest
by Jim Sparks
Maps are (Still) Important Again
Jobs
Applications Programmer Analyst II for Southern Nevada Health District at Las Vegas, Nevada
Applications Programmer Analyst I for Southern Nevada Health District at Las Vegas, Nevada
GIS Project Manager for VHB at Wethersfield, Connecticut
Upcoming Events
Smart GEO Expo 2020 at COEX Hall C Republic of Korea Seoul Korea (South) - Aug 19 - 21, 2020
Defense Services Asia (DSA) 2020 at Kuala Lumpur Malaysia - Aug 24 - 27, 2020
IWCE 2020 Conference at Las Vegas Convention Center LAS VEGAS NV - Aug 24 - 28, 2020
ENVI Analytics Symposium (Virtual EAS) at CO - Aug 25 - 27, 2020
University of Denver GIS Masters Degree Online
UAV Expo2020 -Register   & save



© 2020 Internet Business Systems, Inc.
25 North 14th Steet, Suite 710, San Jose, CA 95112
+1 (408) 882-6554 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering EDACafe - Electronic Design Automation TechJobsCafe - Technical Jobs and Resumes  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy PolicyAdvertise